EECS 119 VLSI (2015-2016)

EECS 119 VLSI

(Required for CpE.)
Catalog Data:

EECS 119 VLSI (Credit Units: 4) Design techniques for Very Large Scale Integrated (VLSI) systems and chips. Review CMOS and related process technologies; primitives such as logic gates and larger design blocks; layout; floor planning; design hierarchy; component interfaces; use of associated CAD tools for design. Prerequisite: EECS112/CSE132; EECS170B. Only one course from EECS 119, CSE 112, EECS 170D may be taken for credit. (Design units: 4)

Required Textbook:
. Edition, , 1969, ISBN-13 978-0130909961.

Recommended Textbook:
None
References:

Weste and Eshraghian, Principles of CMOS VLSI, 2nd Edition, Addison-Wesley, 1994.

Coordinator:
Fadi Kurdahi
Relationship to Student Outcomes
This course relates to Student Outcomes: EAC a, EAC b, EAC e, EAC k.
Course Learning Outcomes. Students will:

1. Design circuits that perform combinational and sequential functions and analyze their performance when implemented in ICs. (EAC a, EAC b, EAC e, EAC k)

2. Design VLSI layouts, analyze, and optimize or tradeoff their quality metrics given a set of constraints. (EAC a, EAC b, EAC e, EAC k)

Prerequisites by Topic
  • Building blocks and organization of digital computers
  • Arithmetic, control and memory units
  • Basic electronics: resistors, capacitors, MOS & bipolar transistors
  • Circuit analysis
Lecture Topics:
  • Introduction.
  • Review, diode, MOSFET Static and dynamic behavior.
  • Inverter, Static CMOS and Dynamic CMOS.
  • Combinational Logic Design. Design of Sequential Circuits.
  • Design of Arithmetic Building Block
  • Timing Issues.
Class Schedule:

Meets for 3 hours of lecture and 1 hour of discussion each week for 10 weeks.

Computer Usage:

MAGIC, IRSIM, SPICE (or equivalent)

Laboratory Projects:

Spice simulation, layout for inverter, layout for basic gates, layout for adder.

Professional Component

Contributes towards the Computer Engineering major requirements for Engineering Topics courses.

Design Content Description
Approach:

Study of devices; diode, transistor, NMOS and PMOS; and the design of: Inverter, Combinational, Clock skew, ALU, Memory.

Lectures: 50%
Laboratory Portion: 50%
Grading Criteria:
  • Homework: 10%
  • Projects: 35%
  • Midterm Exam : 25%
  • Final Exam: 30%
  • Total: 100%
Estimated ABET Category Content:

Mathematics and Basic Science: 0.0 credit units

Computing: 0.0 credit units

Engineering Topics: 4.0 credit units

Engineering Science: 0.0 credit units

Engineering Design: 4.0 credit units

Prepared:
August 6, 2014
Senate Approved:
April 29, 2013
Approved Effective:
2013 Fall Qtr