EECS 117 Parallel Computer Systems (2012-2013)

EECS 117 Parallel Computer Systems

(Not required for any major. Selected Elective for CSE and CpE.)
Catalog Data:

EECS 117 Parallel Computer Systems (Credit Units: 3) General introduction to parallel computing focusing on parallel algorithms and architectures. Parallel models: Flynn's taxomony, dataflow models. Parallel architectures: systolic arrays, hypercube architecture, shared memory machines, dataflow machines, reconfigurable architectures. Parallel alagorithms appropriate to each machine type area also discussed. Prerequisite: EECS20 and EECS112/CSE132. (Design units: 1)

Required Textbook:
. Edition, , 1969, ISBN-13 978-1558603431.

Recommended Textbook:
Jean-Luc Gaudiot
Relationship to Student Outcomes
This course relates to Student Outcomes: EAC a, EAC b, EAC c, EAC d, EAC e, EAC k.
Course Learning Outcomes. Students will:

1. Develop the capability to study the complexity of the problem of parallel processing, from high-level language programming to low-level implem-entation of synchronization principles. (EAC a, EAC b, EAC c, EAC d, EAC e, EAC k)

2. Develop a working knowledge of the design of shared-memory systems, with a particular emphasis on cache coherence mechanisms and memory consistency. (EAC a, EAC b, EAC c, EAC d, EAC e, EAC k)

3. Describe the design of modern interconnection networks. (EAC a, EAC b, EAC c, EAC e, EAC k)

4. Develop an in-depth understanding of message-passing concepts and modern multiprocessor systems. (EAC a, EAC b, EAC c, EAC d, EAC e, EAC k)

5. Develop the knowledge of new models such as functional programming, data-flow execution, reconfigurable architectures, etc. (EAC a, EAC b, EAC c, EAC d, EAC e, EAC k)

Prerequisites by Topic
  • Familiarity with building blocks and organization of digital computers.
  • Knowledge of the arithmetic, control and memory units, and input/out devices.
  • Advanced programming concepts for system software including data types, points, recursion, and modules.
Lecture Topics:
  • Flynn’s taxonomy.
  • Dataflow models.
  • Interconnection networks.
  • Message-passing multiprocessors.
  • Shared memory machines.
  • Dataflow machines.
  • Reconfigurable architectures.
  • Vector processors.
Class Schedule:

Meets for 3 hours of lecture each week for 10 weeks.

Computer Usage:


Laboratory Projects:


Professional Component

Contributes toward the Computer Engineering Topics courses and Major design experience.

Design Content Description

The architecture principles studied in this class are firmly based upon an array of technological and basic design principles.

Lectures: 100%
Laboratory Portion: 0%
Grading Criteria:
  • Home work assignments: 25%
  • Midterm exam: 30%
  • Final exam: 45%
  • Total: 100%
Estimated ABET Category Content:

Mathematics and Basic Science: 0.0 credit units

Computing: 3.0 credit units

Engineering Topics: 3.0 credit units

Engineering Science: 2.0 credit units

Engineering Design: 1.0 credit units

February 6, 2012
Senate Approved:
February 23, 2004
Approved Effective:
2004 Fall Qtr