EECS 112L Organization of Digital Computers Laboratory (2014-2015)

EECS 112L Organization of Digital Computers Laboratory

(Required for CSE and CpE.)
Catalog Data:

EECS 112L Organization of Digital Computers Laboratory (Credit Units: 3) Specification and implementation of a processor-based system using a hardware description language such as VHDL. Hands-on experience with design tools including simulation, synthesis, and evaluation using testbenches. Prerequisite: EECS112/CSE132. Computer Engineering and Computer Science majors have first consideration for enrollment. Same as CSE 132L. (Design units: 3)

Required Textbook:
. Edition, , 1969, ISBN-13 978-0123747501.

Recommended Textbook:
None
References:

Course website: http://e3.uci.edu

Coordinator:
Pai Chou
Relationship to Student Outcomes
This course relates to Student Outcomes: CAC a, CAC i, EAC a, EAC e, EAC i, EAC j, EAC k.
Course Learning Outcomes. Students will:

1. Write structured, multi-module hardware models in VHDL. (CAC a, CAC i, EAC a, EAC e, EAC i, EAC j, EAC k)

2. Compile VHDL files using a CAD tool such as Cadence NCVHDL that involve external libraries. (CAC a, CAC i, EAC a, EAC e, EAC i, EAC j, EAC k)

3. Test and debug programs using a simulator such as Cadence. (CAC a, CAC i, EAC a, EAC e, EAC i, EAC k)

4. Analyze waveforms for correctness and efficiency. (CAC a, CAC i, EAC a, EAC e, EAC i, EAC j, EAC k)

Prerequisites by Topic
  • Fundamentals of Programming (EECS12, 20, 40).
  • Computer architecture, with assembly programming (EECS112).
Lecture Topics:
  • VHDL introduction and basic behavioral modeling. (2 weeks)
  • Structural VHDL and memory modeling. (2 weeks)
  • MIPS ISA simulation and instruction decoding. (2 weeks)
  • Latched-based design and multi-cycle CPU. (2 weeks)
  • Pipelined design and integration. (2 weeks)
Class Schedule:

Meets for 1 hour of lecture, 1 hour of discussion and 3 hours of laboratory each week for 10 weeks.

Computer Usage:

The Sun Sparc server (east.ece.uci.edu) connected to 30 SunRay clients. Also possible to use any X-terminal to remote-login to the server. NCVHDL from Cadence is used as the default software. A fall-back option is ModelSim from Mentor Graphics (runs on Windows or Linux). Another fall-back option is from Synopsys. SPIM from University of Wisconsin is also used (multi-platform).

Laboratory Projects:
  • Assembly programming exercises to familiarize with MIPS ISA, correlate with high-level language constructs.
  • Refining VHDL model for MIPS processor to learn about datapath and control, and integrate the components.
  • Understand timing diagrams and express the intended behavior in VHDL.
  • Latch-based design.
Professional Component

Contributes toward the Computer Engineering and Computer Science and Engineering Computing and Engineering Topics Courses and Major Design experience.

Design Content Description
Approach:

Six weeks of this course are devoted to processor design, two weeks are devoted to structural modeling, and two weeks are devoted behavioral modeling. The understanding of a non-pipelined processor model in a hardware description language, and exercises in the corresponding instruction set architecture. Conversion of the data path to a multi-cycle implementation by register insertion. Techniques for resolving pipeline hazards including bypass and stalling logic. Design of a component with interfaces, such as memory modules or peripheral devices.

Lectures: 30%
Laboratory Portion: 70%
Grading Criteria:
  • Labs: 35%
  • Participation: 10%
  • Final project: 15%
  • Final exam: 40%
  • Total: 100%
Estimated ABET Category Content:

Mathematics and Basic Science: 0.0 credit units

Computing: 3.0 credit units

Engineering Topics: 3.0 credit units

Engineering Science: 0.0 credit units

Engineering Design: 3.0 credit units

Prepared:
June 24, 2014
Senate Approved:
May 9, 2014
Approved Effective:
2014 Fall Qtr