CSE 31L Introduction to Digital Logic Laboratory (2014-2015)

EECS 31L Introduction to Digital Logic Laboratory

(Required for CSE, CpE and EE.)
Catalog Data:

EECS 31L Introduction to Digital Logic Laboratory (Credit Units: 3) Introduction to common digital integrated circuits: gates, memory circuits, MSI components. Operating characteristics, specifications, and applications. Design of simple combinational and sequential digital systems such as arithmetic processors game-playing machines. Construction and debugging techniques, using CAD tools and Breadboards. Prerequisite: EECS31/CSE31; EECS10, EECS12, CSE42/ICS32 or CSE22/ICS22 . Computer Engineering, Computer Science and Engineering, and Electrical Engineering majors have first consideration for enrollment. Same as CSE 31L. (Design units: 3)

Required Textbook:
. Edition, , 1969, ISBN-13 978-0470052631.

Recommended Textbook:
None
References:
None
Coordinator:
Nader Bagherzadeh
Relationship to Student Outcomes
No student outcomes specified.
Course Learning Outcomes. Students will:
Prerequisites by Topic
  • Advanced programming concepts including data types, pointers, recursion and modules.
  • Specifications of digital component with Boolean algebra, FSM and FSMD models
  • Analysis and optimization of register-transfer-level (RTL) components.
  • Standard RTL components, such as adders, decoders, selectors, registers, register files, memories and their use.
  • Introduction to RTL designs with datapath and controller
Lecture Topics:
  • Xilinx ISE tutorial and introduction to simulation (week 1)
  • Logic gates and introduction to VHDL (week 2)
  • Behavioral and structural models of combinational components (week 3)
  • FSM design with behavioral and structural modeling (week 4)
  • FSM synthesis from behavior to structure (week 5)
  • FSMD design and modeling (week 6)
  • RTL designs with datapaths and controllers. (week 7)
  • RTL methodology: from behavior to structure (week 8)
  • IP design and modeling. (week 9)
  • Final Project: DCT (week 10)
Class Schedule:

Meets for 2 hours of lecture and 3 hours of laboratory each week for 10 weeks.

Computer Usage:

Xilinx Foundation series and ModelSim simulating

Laboratory Projects:
  • BeltWarn design (with logic gates),
  • Finite-state machine design (with state-register and combinatorial logic),
  • Vector adder (with datapath and controller),
  • IP design for DCT (with a signal-processing datapath and controller)
Professional Component

Contributes toward the Computer Engineering, Computer Science and Engineering, and the Electrical Engineering Topics Courses and Major Design experience.

Design Content Description
Approach:

Following a brief review of combinational and sequential logic circuits, the class is devoted to register-transfer-level design using VHDL programming, and simulation.

Lectures: 40%
Laboratory Portion: 60%
Grading Criteria:
  • Labs: 70%
  • Final exam: 30%
  • Total: 100%
Estimated ABET Category Content:

Mathematics and Basic Science: 0.0 credit units

Computing: 3.0 credit units

Engineering Topics: 3.0 credit units

Engineering Science: 0.0 credit units

Engineering Design: 3.0 credit units

Prepared:
May 15, 2015
Senate Approved:
January 28, 2013
Approved Effective:
2013 Fall Qtr