CSE 31 Introduction to Digital Systems (2013-2014)

CSE 31 Introduction to Digital Systems

(Required for CpE and EE.)
Catalog Data:

CSE 31 Introduction to Digital Systems (Credit Units: 4) Digital representation of information. Specification, analysis, design and optimization of combinational and sequential logic, register-transfer components and register-transfer systems with datapaths and controllers. Introduction to high-level and algorithmic state-machines and custom processors. Prerequisite: EECS10, EECS12, MAE10, CSE41, ICS31, CSE21/ICS21 or ICSH21. Computer Engineering, Computer Science and Engineering, Electrical Engineering majors have first consideration for enrollment. Same as EECS 31. (Design units: 2)

Required Textbook:
. Edition, , 1969, ISBN-13 978-0470531082.

Recommended Textbook:
None
References:
None
Coordinator:
Daniel D. Gajski
Relationship to Student Outcomes
This course relates to Student Outcomes: CAC a, CAC c, EAC a, EAC b, EAC c, EAC e.
Course Learning Outcomes. Students will:

1. Manipulate or design processing of information in binary form. (CAC a, CAC c, EAC a, EAC b, EAC c, EAC e)

2. Manipulate or design number representation in binary form. (CAC a, EAC b, EAC c, EAC e)

3. Manipulate or design basic combinational and sequential operators and circuits. (CAC a, CAC c, EAC b, EAC c, EAC e)

4. Manipulate or design combination of operators to form register transfer functions and structures, including controllers, datapath, and simple processors. (CAC a, CAC c, EAC b, EAC c, EAC e)

Prerequisites by Topic

Knowledge of computational methods and structured programs in electrical and computer engineering.

Lecture Topics:
  • Number representation and binary codes. (week 1)
  • Combinational logic design principles. (week 3)
  • Combinational logic design practices. (week 4)
  • Review and midterm. (week 5)
  • Introduction to sequential logic, flip-flops, states. (week 6)
  • Sequential logic design principles. State machines. (week 7)
  • Sequential logic design practices. (week 8)
  • Standard RTL(cycle-accurate) modules and networks. (week 9)
  • FSMD, Datapath and control. (week 10)
Class Schedule:

Meets for 3 hours of lecture and 1 hour of discussion each week for 10 weeks.

Computer Usage:

Basic computer skills

Laboratory Projects:

See EECS 31L

Professional Component

Contributes toward the Electrical Engineering, Computer Engineering, and the Computer Science and Engineering, Topics Courses and Major Design experience.

Design Content Description
Approach:

The first weeks of this course are devoted to numbers and gates. The remainder of the session provides instruction in the design of: Combinational circuits. Repister-transfer circuits, ALUs, multipleers, encoders, decoders, MUXes, DEMUXes. Sequential circuit, counters, repisters, repister files, finite state machines.

Lectures: 100%
Laboratory Portion:
Grading Criteria:
  • Homework: 20%
  • Midterm 1: 25%
  • Midterm 2: 25%
  • Final Exam: 30%
  • Total: 100%
Estimated ABET Category Content:

Mathematics and Basic Science: 0.0 credit units

Computing: 4.0 credit units

Engineering Topics: 4.0 credit units

Engineering Science: 2.0 credit units

Engineering Design: 2.0 credit units

Prepared:
May 28, 2013
Senate Approved:
January 8, 2013
Approved Effective:
2013 Fall Qtr